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| ltc2246h 1 2246hfb l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications description 14-bit, 25msps 125c adc in lqfp the ltc ? 2246h is a 14-bit 25msps, low power 3v a/d converter designed for digitizing high frequency, wide dynamic range signals. the ltc2246h is perfect for demanding imaging and communications applications with ac performance that includes 74.5db snr and 90db sfdr. dc specs include 1lsb inl (typ), 0.5lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.6v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. typical inl, 2v range n sample rate: 25msps n C40c to 125c operation n single 3v supply (2.8v to 3.5v) n low power: 75mw n 74.5db snr n 90db sfdr n no missing codes n flexible input: 1v p-p to 2v p-p range n 575mhz full power bandwidth s/h n clock duty cycle stabilizer n shutdown and nap modes n pin compatible family ltc2246h (14-bit), ltc2226h (12-bit) n 48-pin (7mm 7mm) lqfp package n automotive n industrial n wireless and wired broadband communication C + input s/h correction logic output drivers 14-bit pipelined adc core clock/duty cycle control flexible reference d13 ? ? ? d0 clk refh refl analog input 2246h ta01 ov d d ogn d code 0 C2.0 inl error (lsb) C1.0 C0.5 0 2.0 1.0 4096 8192 2246h ta01b C1.5 1.5 0.5 12288 16384 typical application
ltc2246h 2 2246hfb package/order information converter characteristics absolute maximum ratings supply voltage (v dd ) ..................................................4v digital output ground voltage (ognd) ........ C0.3v to 1v analog input voltage (note 3) .......C0.3v to (v dd + 0.3v) digital input voltage ......................C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation .............................................1500mw operating temperature range................ C40c to 125c storage temperature range ................... C65c to 150c ov dd = v dd (notes 1, 2) parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error differential analog input (note 5) l C6 1 6 lsb differential linearity error differential analog input l C1 0.5 1 lsb offset error (note 6) l C15 2 15 mv gain error external reference l C3 0.5 3 %fs offset drift 10 v/c full-scale drift internal reference 30 ppm/c external reference 5 ppm/c transition noise sense = 1v 1 lsb rms the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd a in + a in C gnd refh refh refl refl gnd v dd v dd v dd 13 14 15 16 17 18 19 20 21 22 23 24 gnd clk gnd shdn oe gnd d0 d1 d2 d3 d4 gnd 48 47 46 45 44 43 42 41 40 39 38 37 gnd v dd v dd v cm v cm sense mode of d13 d12 d11 gnd gnd d10 d9 d8 gnd ov dd ognd gnd d7 d6 d5 gnd top view lx package 48-lead (7mm s 7mm) plastic lqfp t jmax = 150c, ja = 53c/w order information lead free finish part marking package description temperature range ltc2246hlx#pbf ltc2246lx 48-lead (7mm 7mm) plastic lqfp C40c to 125c lead based finish part marking package description temperature range ltc2246hlx ltc2246lx 48-lead (7mm 7mm) plastic lqfp C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ ltc2246h 3 2246hfb analog input symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 2.8v < v dd < 3.5v (note 7) l 0.5v to 1v v v in, cm analog input common mode (a in + + a in C )/2 differential input (note 7) single ended input (note 7) l l 1 0.5 1.5 1.5 1.9 2 v v i in analog input leakage current 0v < a in + , a in C < v dd l C10 10 a i sense sense input leakage 0v < sense < 1v l C10 10 a i mode mode pin leakage l C10 10 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) dynamic accuracy symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 12.5mhz input 70mhz input l 72 74.5 74.2 73.4 db db db sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 12.5mhz input 70mhz input l 74 90 90 85 db db db sfdr spurious free dynamic range 4th harmonic or higher 5mhz input 12.5mhz input 70mhz input l 78 90 90 90 db db db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 12.5mhz input 70mhz input l 71.5 74.5 74.2 73.4 db db db imd intermodulation distortion f in1 = 4.3mhz, f in2 = 4.6mhz 90 db the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) internal reference characteristics parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/c v cm line regulation 2.8v < v dd < 3.5v 3 mv/v v cm output regulation C1ma < i out < 1ma 4 t a = 25c. (note 4) digital inputs and digital outputs symbol parameter conditions min typ max units logic inputs (clk, oe, shdn) v ih high level input voltage v dd = 3v l 2v v il low level input voltage v dd = 3v l 0.8 v i in input current v in = 0v to v dd l C10 10 a c in input capacitance (note 7) 3 pf the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) ltc2246h 4 2246hfb power requirements symbol parameter conditions min typ max units v dd analog supply voltage (note 9) l 2.8 3 3.5 v ov dd output supply voltage (note 9) l 0.5 3 3.6 v i vdd supply current l 25 30 ma p diss power dissipation l 75 90 mw p shdn shutdown power shdn = h, oe = h, no clk 2 mw p nap nap mode power shdn = h, oe = l, no clk 15 mw the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 8) timing characteristics symbol parameter conditions min typ max units f s sampling frequency (note 9) l 1 25 mhz t l clk low time duty cycle stabilizer off duty cycle stabilizer on (note 7) l l 18.9 5 20 20 500 500 ns ns t h clk high time duty cycle stabilizer off duty cycle stabilizer on (note 7) l l 18.9 5 20 20 500 500 ns ns t ap sample-and-hold aperture delay 0ns t d clk to data delay c l = 5pf (note 7) l 1.4 2.7 6 ns data access time after oe c l = 5pf (note 7) l 4.3 12 ns bus relinquish time (note 7) l 3.3 10 ns pipeline latency 5 cycles the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a l 2.7 2.995 2.99 v v v ol low level output voltage i o = 10a i o = 1.6ma l 0.005 0.09 0.4 v v ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v ltc2246h 5 2246hfb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 25mhz, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code ? ickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 25mhz, input range = 1v p-p with differential drive. note 9: recommended operating conditions. typical performance characteristics typical inl, 2v range, 25msps typical dnl, 2v range, 25msps 8192 point fft, f in = 5mhz, C1db, 2v range, 25msps 8192 point fft, f in = 30mhz, C1db, 2v range, 25msps 8192 point fft, f in = 70mhz, C1db, 2v range, 25msps 8192 point fft, f in = 140mhz, C1db, 2v range, 25msps code 0 inl error (lsb) 12288 2246h g01 4096 8192 16384 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 code 0 dnl error (lsb) 12288 2246h g02 4096 8192 16384 1.00 0.75 0.50 0.25 0 C0.25 C0.50 C0.75 C1.00 frequency (mhz) 0 amplitude (db) 2246h g03 246810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2246h g04 246810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2246h g05 246810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 frequency (mhz) 0 amplitude (db) 2246h g06 246810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 electrical characteristics ltc2246h 6 2246hfb typical performance characteristics 8192 point 2-tone fft, f in = 10.9mhz and 13.8mhz, C1db, 2v range, 25msps grounded input histogram, 25msps snr vs input frequency, C1db, 2v range, 25msps sfdr vs input frequency, C1db, 2v range, 25msps snr and sfdr vs sample rate, 2v range, f in = 5mhz, C1db snr vs input level, f in = 5mhz, 2v range, C1db sfdr vs input level, f in = 5mhz, 2v range, 25msps i vdd vs sample rate, 5mhz sine wave input, C1db i ovdd vs sample rate, 5mhz sine wave input, C1db, o vdd = 1.8v frequency (mhz) 0 amplitude (db) 2246h g07 246810 12 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 code 8179 8180 8181 8182 8183 8184 8185 8186 3227 278 18803 22016 853 6919 43 count 2246h g08 25000 20000 15000 10000 5000 0 13373 input frequency (mhz) 0 snr (dbfs) 200 2246h g09 50 100 150 75 74 73 72 71 70 input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 2246h g10 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 2246h g11 10 20 30 40 50 snr sfdr input level (dbfs) snr (dbc and dbfs) 2246h g12 80 70 60 50 40 30 20 10 0 C60 C40 C50 C20 C30 C10 0 dbc dbfs input level (dbfs) C60 C50 C40 C20C30 C10 0 2246h g13 sfdr (dbc and dbfs) 120 110 100 90 80 70 60 50 40 30 20 dbfs dbc 90dbc sfdr reference line sample rate (msps) i vdd (ma) 2246h g14 35 30 25 20 15 0 10 20 515 25 30 35 2v range 1v range 0 10 20 515 25 30 35 sample rate (msps) i ovdd (ma) 2246h g15 3 2 1 0 ltc2246h 7 2246hfb pin functions gnd (pins 1, 4, 9, 13, 15, 18, 24, 25, 29, 32, 36, 37, 48): adc power ground. a in + (pin 2): positive differential analog input. a in C (pin 3): negative differential analog input. refh (pins 5, 6): adc high reference. bypass to pins 7, 8 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pins 7, 8 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. refl (pins 7, 8): adc low reference. bypass to pins 5, 6 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. v dd (pins 10, 11, 12, 46, 47): 3v supply. bypass to gnd with 0.1f ceramic chip capacitors. clk (pin 14): clock input. the input sample starts on the positive edge. shdn (pin 16): shutdown mode selection pin. connecting shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. if the clock duty cycle stabilizer is used, a >1s high pulse should be applied to the shdn pin once the power supplies are stable at power up. oe (pin 17): output enable pin. refer to shdn pin function. d0-d13 (pins 19-23, 26-28, 33-35, 38-40): digital out- puts. d13 is the msb. ognd (pin 30): output driver ground. ov dd (pin 31): positive supply for the output drivers. bypass to ground with 0.1f ceramic chip capacitor. of (pin 41): over/under flow output. high when an over or under ? ow has occurred. mode (pin 42): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin 43): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 44, 45): 1.5v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. ltc2246h 8 2246hfb functional block diagram figure 1. functional block diagram shift register and correction diff ref amp ref buf 2.2f 1f 1f 0.1f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 2246h f01 input s/h sense v cm a in C a in + 2.2f third pipelined adc stage output drivers control logic shdn of d13 d0 ? ? ? ltc2246h 9 2246hfb timing diagram t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n C 4 n C 3 n C 2 n C 1 clk d0-d13, of 2246h td01 n C 5 n ltc2246h 10 2246hfb dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamen- tal input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the ? rst ? ve harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 + ...vn 2 () /v1 () where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the ? fth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodulation distortion applications information is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spuri- ous noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) converter operation as shown in figure 1, the ltc2246h is a cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value ? ve cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2246h has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the ltc2246h 11 2246hfb applications information dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h dur- ing this high phase of clk. when clk goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and ? fth stages, resulting in a ? fth stage residue that is sent to the sixth stage adc for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2246h cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, figure 2. equivalent input circuit the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to v cm or a low noise reference voltage between 1v and 1.5v. common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pins (pins 44, 45) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pins must be bypassed to ground close to the adc with a 2.2f or greater capacitor. v dd v dd 15 15 c parasitic 1pf c parasitic 1pf c sample 4pf c sample 4pf ltc2246h a in + a in C clk 2246h f02 ltc2246h 12 2246hfb input drive impedance as with all high performance, high speed adcs, the dy- namic performance of the ltc2246h can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can in? uence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2246h being driven by an rf transformer with a center tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the trans- former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the sfdr at high input frequencies. figure 5 shows a single-ended input circuit. the impedance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. applications information figure 3. single-ended to differential conversion using a transformer figure 4. differential drive with an ampli? er figure 5. single-ended drive 25 25 25 25 0.1 f a in + a in C 12pf 2.2f v cm ltc2246h analog input 0.1 f t1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 p ackage size 2246h f03 25 25 12pf 2.2f v cm ltc2246h 2246h f04 C C + + cm analog input high speed differential amplifier a in + a in C 25 0.1 f analog input v cm a in + a in C 1k 12pf 2246h f05 2.2f 1k 25 0.1 f ltc2246h ltc2246h 13 2246hfb reference operation figure 6 shows the ltc2246h reference circuitry consist- ing of a 1.5v bandgap reference, a difference ampli? er and switching and control circuit. the internal voltage reference can be con? gured for two pin selectable input ranges of 2v (1v differential) or 1v (0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference ampli? er to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference ampli? er generates the high and low reference for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in figure 7. an external reference can be used by apply- ing its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1f ceramic capacitor. input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise performance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5.8db. applications information figure 6. equivalent reference circuit figure 7. 1.5v range adc figure 8. clk drive using an lvds or pecl to cmos converter v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ? v sense for 0.5v < v sense < 1v 1.5v refl 2.2f 2.2f internal adc high reference buffer 0.1f 2246h f06 ltc2246h 4 diff amp 1f 1f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control v cm sense 1.5v 0.75v 2.2f 12k 1f 12k 2246h f07 ltc2246h clk 100 0.1f 4.7f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 2246h f08 ltc2246h ltc2246h 14 2246hfb driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a differential clock can also be used along with a low-jitter cmos converter before the clk pin (see figure 8). the noise performance of the ltc2246h can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. maximum and minimum conversion rates the maximum conversion rate for the ltc2246h is 25msps. for the adc to operate properly, the clk signal should have a 50% (5%) duty cycle. each half cycle must have at least 18.9ns for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. if the clock duty cycle stabilizer is used, a >1s high pulse should be applied to the shdn pin once the power supplies are stable at power up. the lower limit of the ltc2246h sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2246h is 1msps. digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits, and the over? ow bit. digital output buffers figure 9 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2246h should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. applications information table 1. output codes vs input voltage a in + C a in C (2v range) of d13 C d0 (offset binary) d13 C d0 (2s complement) >+1.000000v +0.999878v +0.999756v 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122v 0.000000v C0.000122v C0.000244v 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.999878v C1.000000v ltc2246h 16 2246hfb package description lx package 48-lead plastic lqfp (7mm 7mm) (reference ltc dwg # 05-08-1760 rev ?) lx48 lqfp 0907 rev? 0 C 7 11 C 13 0.45 C 0.75 1.00 ref 11 C 13 9.00 bsc aa 7.00 bsc 1 2 7.00 bsc 9.00 bsc 48 1.60 max 1.35 C 1.45 0.05 C 0.15 0.09 C 0.20 0.50 bsc 0.17 C 0.27 gauge plane 0.25 note: 1. package dimensions conform to jedec #ms-026 package outline 2. dimensions are in millimeters 3. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 4. pin-1 indentifier is a molded indentation, 0.50mm diameter 5. drawing is not to scale see note: 4 c0.30 C 0.50 r0.08 C 0.20 7.15 C 7.25 5.50 ref 1 2 5.50 ref 7.15 C 7.25 48 package outline recommended solder pad layout apply solder mask to areas that are not soldered section a C a 0.50 bsc 0.20 C 0.30 1.30 min ltc2246h 17 2246hfb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 02/11 removed tape and reel information from order information 2 (revision history begins at rev b) ltc2246h 18 2246hfb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2007 lt 0211 rev b ? printed in usa related parts part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, C70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion: C94dbc at 1mhz ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2225 12-bit, 10msps, 3v adc, lowest power 60mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2226 12-bit, 25msps, 3v adc, lowest power 75mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2227 12-bit, 40msps, 3v adc, lowest power 120mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2228 12-bit, 65msps, 3v adc, lowest power 205mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2229 12-bit, 80msps, 3v adc, lowest power 211mw, 70.6db snr, 90db sfdr, 32-pin qfn ltc2236 10-bit, 25msps, 3v adc, lowest power 75mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2237 10-bit, 40msps, 3v adc, lowest power 120mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2238 10-bit, 65msps, 3v adc, lowest power 205mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2239 10-bit, 80msps, 3v adc, lowest power 211mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2245 14-bit, 10msps, 3v adc, lowest power 60mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2246 14-bit, 25msps, 3v adc, lowest power 75mw, 74.5db snr, 90db sfdr, 32-pin qfn ltc2247 14-bit, 40msps, 3v adc, lowest power 120mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2248 14-bit, 65msps, 3v adc, lowest power 205mw, 74.3db snr, 90db sfdr, 32-pin qfn ltc2249 14-bit, 80msps, 3v adc, lowest power 222mw, 73db snr, 90db sfdr, 32-pin qfn ltc2250 10-bit, 105msps, 3v adc, lowest power 320mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2251 10-bit, 125msps, 3v adc, lowest power 395mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2252 12-bit, 105msps, 3v adc, lowest power 320mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2253 12-bit, 125msps, 3v adc, lowest power 395mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2254 14-bit, 105msps, 3v adc, lowest power 320mw, 72.4db snr, 88db sfdr, 32-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50< single-ended rf and lo ports |
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